Patent US10284824, filed 2017 Jan 22, was granted on 2019 May 7. It describes and protects a concept to break the data volume barrier as we encounter it in ultra-high-speed image sensors. Aggregated pixel rates nowadays exceed 10 Gigapixels/second and require a very high number of parallel electrical channels. Further increase with the present state of the art requires an even higher degree of parallelism, which soon becomes unrealistic.
Caeleste’s concept avoids the huge electrical parallelism. Data are output through an extra “photonic layer”, 3D-integrated below the image sensor IC. This layer interfaces directly with fiber optic transmission lines.
You can download the patent from here.
The patent idea was previously presented at IS Americas, from which the presentation can be found here.