Caeleste is strengthening its business development team by hiring Jeroen Hoet as new Chief Business Development Officer, leading Caeleste’s marketing and sales department. Based in Belgium, Jeroen is well known in the semiconductor industry and has gained deep knowledge on vision technologies and custom chip design through similar positions at leading machine vision and ASIC design companies. (more…)
Caeleste patents a true charge domain binning method
Thereby removing the second last (*) stronghold of CCD as compared to CMOS.
The purpose of binning is to collect the photo charges of a small kernel of pixels into a single charge packet, reading it out in a single operation. Caeleste patents a method to do this. Read more
The Mars Webcam Interview: development, challenges and unique features of a camera in space
Caeleste and Advacam announced their collaboration on the development of a Hybrid Visible CMOS image sensor for future space and science missions.
The combination of Advacam’s advanced capabilities in hybridization of Silicon on Silicon and Caeleste’s image sensor know-how for space applications allows ESA to start the project AO/1-9801/19/NL/AR “Development of a Hybrid Visible Image Sensor”. Hybrid image sensor technology makes the best of both worlds available; it offers the ability to independently customize the performance of both the ROIC and the detection layer from soft X-rays over ultraviolet to near-infrared.
ESA wants to develop and safeguard the hybrid Silicon-on-Silicon technology. It is expected that such detector would have a wide range of applications for Earth observation, as well as astronomy and planetary applications.
Operational continuity at Caeleste while implementing the governmental measures to contain COVID-19.
Caeleste remains open and operational.
As always, we assure our commitment to our partners, while bound to follow government instructions.
We are currently not visiting any customers or trade fairs. All communications continue via email, telephone or video conferencing.
The Caeleste team
HDR cameras for space
An earlier news item demonstrated ELFIS first “true HDR” movie.
Read more on the ESA website about the Technology Development Element activity with LFoundry (Italy) and Airbus (France) and find out about more interesting features of the “European Low Flux Image Sensor”
Patent “Enhanced dynamic range imaging” granted
US patent US10.497.737 entitled “enhanced dynamic range imaging” was granted on Dec 3, 2019.
It describes a pixel and methods to reach a very high dynamic range (HDR) by integrating the same photo charge on multiple capacitors synchronously. The concept reminds other Caeleste HDR methods (patents US9.780.138, US9.699.398, US9.819.882, BE1023468), yet uses a conceptually different approach.
Creative Collaboration resulted in a new paradigm in neural recording
Our expertise on low noise readout circuits lead to the collaboration with the Californian med-tech startup Paradromics. Caeleste developed a Read-Out Integrated Circuit system for a neural sensor which has an extremely challenging noise requirement to be able to read the neuron potentials. This is where our passion for technological challenges and craftsmanship was crucial for the success of the sensor development. Read the full article here:
Crane needed to move climate chamber into the Caeleste characterization lab.
We know what matters for our tests: reliable, precise and reproducible results. When testing sensors, you must adhere to numerous test standards and carry out long-term tests.
The LabEvent T/210/70/3 (WeissTechnik) climate chamber allows to cool or heat the environment down to -70°C or up to +180°C. To avoid condensation and formation of ice, nitrogen is flushed. It can contain setups or instruments as large as 630x560x570 mm.
Caeleste will be presenting three papers at CMOS Image Sensors Workshop – Toulouse 26 & 27 November 2019
At the annual “Space & Scientific CMOS Image Sensors” workhop, Toulouse on November 26th and 27th 2019, Caeleste will present three papers. A fourth paper where Caeleste is co-author is presented by CSEM. The Toulouse workshop is considered as the most prominent space image sensor conference in Europe.
The slides will be made available on this website after the workshop.
1. A rad-hard, global shutter, true HDR, backside illuminated image sensor
by B.Dierickx1, A. Kalgi1, D. Van Aken1, A. Klekachev1, J. Basteleus1, P. Stampoglis1, G. Di Nicolantinio2, F. Palumbi2, A. Pelamatti3 of 1Caeleste, 2LFoundry, and 3Airbus
The ELFIS (ESA contract 4000116089) is the first image sensor that combines following properties: True HDR or “MAF HDR” (Motion Artifact Free High Dynamic Range), IWR Global shutter using GS CMOS technology, BSI (Backside illumination) and TID (total ionizing dose) radiation hard design. It has 1920×1024 pixels on a 15µm pitch. We will describe the design, the measured key performance parameters and show recorded movies demonstrating the high dynamic range (96dB) while operating in IWR global shutter.
See also previous posts: movie and white paper.
2. Hyperspectral CMOS BSI Image sensor
By Deepraj Gautam1, Qiang Yao1, Dirk van Aken1, Bart Dierickx1, Bert Luyssaert1, Wei Wang1, Dirk Uwaerts1, Koen Liekens1, Gaozhan Cai1, Kyriaki Minoglou2, Arnaud Bourdoux3, Dominique Baudoux3, Vincent Moreau4, Eric Callut5, Julien Nuttin5 of Caeleste (1), ESA (2), (3) Spacebel, (4) AMOS, (5) Deltatec
The “Enhanced Light Offner Image Sensor” (ELOIS) is a 2048 x 256 hyperspectral CMOS BSI image sensor, developed with the support of the European Space Agency. The sensor has a broad spectral range from 400nm to 1000nm. The pixel size is 15.5 x 15.5 µm2. The peak quantum efficiency is 95%. The full well capacity of one pixel can be programmed between 40ke- and 200ke-. Pixels can be 4×1 binned.
Proton damage resilient pixels
An interesting feature of ELOIS is its “proton resilient” pixel. Groups of 4×1 (sub-)pixels can be binned in two ways. In charge domain binning, floating diffusions are shunted, and the charge is averaged. In voltage domain binning the source follower sources are shunted, acting as analog “maximum operator”.
3. Optimized ASIC Development for Space Large Format NIR/SWIR Detector Array
by Peng Gao, Andrew Keefe, Bart Dierickx, Qiang Yao, Wei Wang, Tim Morlion*, Bert Van Thielen*, Ramses Valvekens* of Caeleste, Mechelen, Belgium and *EASICS, Leuven, Belgium
We describe the design of a universal, radhard, cryogenic, low power, interfacing ASIC for space-based, large format NIR/SWIR detector arrays. This device is designed for 50krad (TID) ionizing radiation and tolerant for SEE. Planned operation temperature is between 35 and 77 Kelvin.
4. Results of microlens testing on back-illuminated sensors for space
by F. Zanella1, G. Basset1, C. Schneider1, A. Luu-Dinh1, I. Marozau2, S. Fricke1, A. Madrigal2, D. Van Aken3, M. Zahir4, of CSEM(1,2) , CAELESTE(3) and ESTEC (4)
CSEM will present a paper reporting an activity one the design, manufacture and test of microlenses on a back thinned CMOS image sensor under space environment conditions. The validation had to address the microlens technology, its design, materials and involved processes. The image sensor employed was the ELOIS, presented in paper no.2, listed above.