Thereby removing the second last (*) stronghold of CCD as compared to CMOS.
The purpose of binning is to collect the photo charges of a small kernel of pixels into a single charge packet, reading it out in a single operation. Caeleste patents a method to do this by making a number of pixels “non-collecting”. The photo charge that is not collected by these pixels is then collected by drift or diffusion by the other pixels in the kernel.
Traditionally pixels are operated in such way that their photodiodes collect photo charges. The opposite would not be obvious. In the present method however, this is precisely what happens: a number of pixels is operated in such way that they do not, or much less, collect photo charges.
A pixel can be made non- or less collecting by letting the photodiode float, or by biasing it to a lower voltage.
In the schematic cross section in this figure three pixels are shown of which the middle one is “non collecting” by letting its photodiode float.
Photo-electrons drift along the electric field lines to the “collecting” diodes. They capture charge that would normally have flown to the non-collecting diodes.
Figure A is a is a floorplan of a small array of pixels. Traditionally all pixels have charge collecting photodiodes “C”. Figure B: The same pixel array, showing the extension of the charge collection volume around each of the collecting (“C”) pixels. The other pixels are operated to be non-collecting, realizing 2×2 binning. Figure C: The same pixel array, a different configuration of collecting and non-collecting pixels, effectively realizing 3×3 binning.
Schematic cross section through three 4T pixels. The two outer pixels are operated to be collecting, the middle pixel is operated to be not collecting by permanently turning off the transfer gate TG.
Schematic cross section through three 4T pixels. The two outer pixels are operated to be collecting, the middle pixel is operated to be not collecting by letting the supply of the pixel float.
(*) the very last stronghold of CCD is “TDI” (time delay & integration). No decent method to do that in CMOS has been invented yet.