Caeleste News

Two Caeleste papers at IISW 2019

At the International Image Sensor Workshop, June 2019, Utah, USA, Caeleste will present two papers on advanced CMOS image sensors.

Peng Gao, design team leader at Caeleste will present the paper

“16.7Mpixel 8000fps sparse binarized scientific image sensor”

by Peng Gao, Sampsa Veijalainen, Jente Basteleus, Gaozhan Cai, Bert Luyssaert and Bart Dierickx

This is a large format (36.1×40.2 mm2), 4K x 4K CMOS image sensor, having single-bit binary pixels on a 8µm pitch.  By the use of a proprietary readout technique it reaches frame rates up to 8000fps in sparse mode.

 

Annotated photograph of the image sensor

Ajit Kalgi, design team leader at Caeleste, will present the paper

“Fast Charge Transfer in 100µm long PPD Pixels”

by Ajit Kumar Kalgi, Arne Crouwels, Bart Dierickx, Walter Verbruggen and Dirk Van Aken

In this paper we present a patented photodiode structure for fast charge transfer in elongated pixels. For applications requiring high frame rate and elongated pixels, charge diffusion in photodiode limits the transfer efficiency, thus ultimate frame rate. We solve this by creating electrostatic potential gradient in the elongate direction by exploiting the effect of proximity of implanted regions on the pinning voltage.

Measured diffusion time using or not using the technique.

ELFIS first true HDR image

The ELFIS imager is the first image sensor ever combining following features:

  1. True HDR (“MAF HDR”, motion artifact free HDR)
  2. Global shutter using GS technology,
    1. Allowing low noise CDS readout
    2. Enabling Global Shutter (IWR) without dark current penalty
  3. Backside illumination
  4. TDI radiation hard design

It is developed under ESA contract 4000116089 “European Low Flux Image Sensor”, in collaboration with LFoundry (I) and Airbus (F).

The first “true” HDR image of the ELFIS sensor.
Figure: The first “true” HDR image of the ELFIS sensor.

The above image is taken under following conditions

  • Looking through the lab’s window to sunlit buildings at the other side of the street
  • Nikon 55mm lens, diaphragm set to 22 (!)
  • IWR tframe=tint = 30ms
  • On-chip CDS and dark frame subtraction
  • No PRNU correction, no linearization, no bad pixel correction, no other cosmetic corrections.
  • The HDR image is created by a simple threshold at 80% of the HG saturation.
  • The image is “histogram equalized”

Read more

Caeleste in the ESA roadmap

Caeleste was since its creation involved in several long-term developments in the European Space Agency context. As an illustration find below the recent ESA presentation  “CMOS Image Sensor developments supported by the European Space Agency”, by K. Minoglou, at the 2018 EIROForum Topical Workshop.  Several Caeleste collaborations are explicitly mentioned.



Find the original slide show here.

Caeleste at the intoPIX compression workshop

The Sensation project is built upon a consortium of different partners active in sensor development, camera development and compression algorithms and is funded by Penta. Multiple workshops were organized to strengthen the partnership, cooperation and knowledge-sharing between the SENSATION consortium stakeholders.

In broadcast and machine-vision, compression is at the utmost importance to achieve an efficient transmission of high frame rates with UHD HDR (8K) images. The Sensation project strives for a profound cooperation between the camera and image sensor designers and the compression algorithm designers to allow the upmost efficiency in timing, cost and quality of the resulting compressed image in the camera system. Therefore, as part of the Sensation project, intoPIX organized a compression workshop on the 17th of January. Various partners of the consortium will demonstrate their knowledge on image compression on the camera platform. Following speakers kept lectures during this workshop:

  • intoPIX
  • Caeleste (On Chip companding, Arne Crouwels)

Bart Dierickx will present at Pixel 2018, Taipei, Taiwan.

On Friday 14 December 2018 Bart Dierickx, CTO, will present at the Pixel2018 workshop in Taipei, Taiwan, the joint Caeleste & Paradromics paper:

Pixel array for 3-D integration with an intra-cortical electrode array

“Here we present a Read-Out Integrated Circuit (ROIC) with metalized topside contacts that is bonded to an array of insulated microwires to form a platform for in vivo, intra-cortical recording (recording of the brain’s neurons electric potential waveforms) of unprecedented scale.

The pixel consists of an AC-coupled sense-amplifier, followed by an anti-aliasing band filter. It has a metalized top-side contacts on each readout array element (pixel) for bonding to an array of microwire probes. It is measured to have lower than 10μVRMS noise to record action potentials with high fidelity. The pixel size, 50µm, fits the desired inter-wire spacing for the array. It supports full-frame readout beyond 32,000 fps.”

Feel free to contact us if you would like to meet our CTO there.

Caeleste will give a talk at the CNES workshop in Toulouse

On Wednesday 28 November 2018 Dirk Van Aken, Senior Project Manager, will present at the CNES workshop on ultraviolet detectors and instruments in Toulouse (France) the paper:

“QE of front side and back side thinned CMOS Image Sensors between 100 and 400nm”

Classical frontside illuminated CMOS and CCD image sensors are suitable for visible light imaging, yet suffer serious degradation in spectral response for wavelengths especially in the near and deep UV.

The underlying reasons (interference, material-specific absorption, coatings, surface treatments) are fairly well understood, and certain measures to enhance the UV response are possible.

We had the occasion to have virtually the same device processed in following flavours of two CMOS image sensor processes:

  • Plain frontside illumination, with all dielectric layers including the passivation layer in place
  • Frontside illumination with the dielectric stack completely removed
  • Frontside illumination with the dielectric stack partially removed
  • Backside illumination with 3 combinations of Si layer thickness and anti-reflective coatings.